Signal distortion limits the sensitivity and bandwidth of any communication system. A form of distortion commonly referred to as “intersymbol interference” (ISI) is particularly problematic and is manifested in the temporal spreading and consequent overlapping of individual pulses, or “symbols.” Severe ISI prevents receivers from distinguishing symbols and consequently disrupts the integrity of received signals.
FIG. 1 (prior art) depicts a conventional receiver 100, which is used here to illustrate the ISI problem and a corresponding solution. Receiver 100 includes a data sampler 105 and a feedback circuit 110. Sampler 105 includes a differential amplifier 115 connected to a decision circuit 120. Decision circuit 120 periodically determines the probable value of signal Din and, based on this determination, produces a corresponding output signal Dout.
Sampler 105 determines the probable value of signal Din by comparing the input signal Din to a voltage reference Vref at a precise instant. Unfortunately, the effects of ISI depend partly on the transmitted data pattern, so the voltage level used to express a given logic level varies with historical data patterns. For example, a series of logic zero signals followed by a logic one signal produces different ISI effects than a series of alternating ones and zeroes. Feedback circuit 110 addresses this problem using a technique known as Decision Feedback Equalization (DFE), which produces a corrective feedback signal that is a function of received historical data patterns.
DFE feedback circuit 110 includes a shift register 125 connected to the inverting input of amplifier 115 via a resistor ladder circuit 130. In operation, receiver 100 receives a series of data symbols on an input terminal Din, the non-inverting input terminal of amplifier 115. The resulting output data Dout from sampler 105 is fed back to shift register 125, which stores the prior three output data bits. (As with other designations herein, Din and Dout refer to both signals and their corresponding nodes; whether a given designation refers to a signal or a node will be clear from the context.)
Shift register 125 includes a number of delay elements, three flip-flops D1-D3 in this example, that apply historical data bits to the reference voltage side of the differential amplifier 115 via respective resistors R1, R2, and R3. The value of each resistor is selected to provide appropriate weight for the expected effect of the corresponding historical bit. In this example, the value of resistor R3 is high relative to the value of resistor R1 because the effect of the older data (D3) is assumed to be smaller than the effect of the newer data (D1). For the same reason, the resistance of resistor R2 is between the resistors R1 and R3. Receiver 100 includes a relatively simple DFE circuit for ease of illustration: practical DFE circuits may sample more or fewer historical data values. For a more detailed discussion of a number of receivers and DFE circuits, see U.S. Pat. No. 6,493,394 to Tamura et al., issued Dec. 10, 2002, which is incorporated herein by reference.
The importance of accurate data reception motivates receiver manufacturers to characterize carefully their system's ability to tolerate ISI and other types of noise. One such test, a so-called “margin” test, explores the range of voltage and timing values for which a given receiver will properly recover input data.
FIG. 2 depicts a fictional eye pattern 200 representing binary input data to a conventional receiver. Eye pattern 200 is graphed in two dimensions, voltage V and time T. The area of eye 205 represents a range of reference voltages and timing parameters within which the data represented by eye 205 will be captured. The degree to which the voltage V and time T of the sampling point can vary without introducing an error is termed the “margin.”
FIGS. 3A through 3C depict three signal eyes 300, 305, and 310 illustrating the effects of DFE on margins and margin testing. Referring first to FIG. 3A, eye 300 approximates the shape of eye 205 of FIG. 2 and represents the margin of an illustrative receiver in the absence of DFE. FIG. 3B represents the expanded margin of the same illustrative receiver adapted to include DFE: the DFE reduces the receiver's ISI, and so extends the margins beyond the boundaries of eye 300. Increasing the margins advantageously reduces noise sensitivity and improves bit error rates (BER).
In-system margin tests for a receiver are performed by monitoring receiver output data (e.g., Dout in FIG. 1) while varying the reference voltage and sample timing applied to the input waveform Din. With reference to FIG. 2, such testing samples various combinations of voltage and time to probe the boundaries of eye 205, the boundaries being indicated when the output data does not match the input data. Margin tests thus require the receipt of erroneous data to identify signal margins. Zerbe et al. detail a number of margin tests in “Method and Apparatus for Evaluating and Optimizing a Signaling System,” U.S. patent application Ser. No. 09/776,550, which is incorporated herein by reference.
A particular difficulty arises when determining the margins of DFE-equipped receivers. While feeding back prior data bits increases the margin (FIG. 3B), the effect is just the opposite if the feedback data is erroneous. Erroneous feedback emphasizes the ISI and consequently reduces the margin, as shown in FIG. 3C. The margin of a DFE-equipped receiver thus collapses when a margin test begins to probe the limits of the test signal (e.g., the boundaries of eye 205). The incompatible requirements of erroneous data for the margin test and correct data for the DFE thus impede margin testing. There is therefore a need for improved means of margin testing DFE-equipped receivers.
The need for accurate margin testing is not limited to DFE-equipped receivers. Errors in margin testing lead integrated-circuit (IC) designers to specify relatively large margins of error, or “guard bands,” to ensure that their circuits will perform as advertised. Unfortunately, the use of overly large margins reduces performance, an obvious disadvantage in an industry where performance is paramount. There is therefore a need for ever more precise methods and circuits for accurately characterizing the margins of high-speed integrated circuits.